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Staff Engineer, VLSI Design Engineering (SOC, Verification, UVM)
Job description
Job responsibilities:
- Develop test plans, tests and verification infrastructure for a complex IP/Sub-System or lead major deliverables for SoC
- Create verification environment using UVM methodology
- Hands on in end to end Logic Verification Process including Verification Planning, Functional Coverage planning and development, Test case development, regression, debug and Coverage closure
- Create reusable bus functional models, monitors, checkers and scoreboards
- Drive functional coverage driven verification closure.
- Work with architects, designers, and post-silicon teams
- Hands-on contributions to SVA development like coding, porting and maintaining System Verilog Assertions including Formal Verification
- Development of tools for Design and Verification support
- Debug failures and root-cause it by interacting with other teams/groups Etc.
Required skills
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Company information
- Company
- Sandisk
- Location
-
India, Karnataka, Bangalore
India - Posted
- 8 months ago
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