(Sr.) ISP RTL Design Manager

Responsibilities Responsible for implementing ISP Algorithm into HW using Verilog, SystemVerilog and/or SystemC (High Level Synthesis) Define ISP HW Architecture based on product features and performance requirements, also with gate count and power estimation Verify Logic at ISP level and Digital System level Optimize Design for less gate count and low power consumption Drive ISP Design activities in close collaboration with ISP Algorithm Team, ISP Design leaders in other sites, and Digital Systems Engineers Ensure compliance with ISP design guidelines and standards Coordinate with cross-functional teams to ensure timely delivery of ISP RTL designs Provide technical guidance and support to junior engineers and interns on ISP RTL design tasks Develop and maintain ISP RTL design tools and scripts as needed