Gate Level Simulations Jobs

Explore 3 active Gate Level Simulations job openings aggregated from hundreds of sources. Roles range from entry-level to executive, remote and on-site, refreshed hourly.

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DFT Engineers

ACL Digital India, Karnataka, Bangalore IN 7 months ago

DFT Engineer Job Description: Scan insertion. SCAN DRC/Coverage debug. ATPG Pattern generation. Gate level simulations ( Zero delay/Timing Delay simulations). Worked on JTAG/P1500 protocols. Perl/Tcl...

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Sr./ Lead Design Verification

ACL Digital India, Karnataka, Bangalore IN 1 year ago

Experience: 4 to 12 Years.Location: Bangalore.Must have hands-on experience coding in System Verilog/UVM.Experience developing testbenches for block level or IP level verification.Experience working o...

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Sr./ Lead Design Verification

ACL Digital India, Karnataka, Bangalore IN 1 year ago

Experience: 4 to 12 Years.Location: Bangalore.Must have hands-on experience coding in System Verilog/UVM.Experience developing testbenches for block level or IP level verification.Experience working o...

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