3 active jobs
Explore 3 active Gate Level Simulations job openings aggregated from hundreds of sources. Roles range from entry-level to executive, remote and on-site, refreshed hourly.
3 jobs · newest first
ACL Digital India, Karnataka, Bangalore IN
DFT Engineer Job Description: Scan insertion. SCAN DRC/Coverage debug. ATPG Pattern generation. Gate level simulations ( Zero delay/Timing Delay simulations). Worked on JTAG/P1500 protocols. Perl/Tcl...
ACL Digital India, Karnataka, Bangalore IN
Experience: 4 to 12 Years. Location: Bangalore. Must have hands-on experience coding in System Verilog/UVM. Experience developing testbenches for block level or IP level verification. Experience worki...
ACL Digital India, Karnataka, Bangalore IN
Experience: 4 to 12 Years. Location: Bangalore. Must have hands-on experience coding in System Verilog/UVM. Experience developing testbenches for block level or IP level verification. Experience worki...
Sign up to save jobs, get personalized alerts, and tailor your CV for better matches.