L&T Technology Services
1 month ago
Senior DV Engineers (UVM/Verilog)
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Company information
- Company
- L&T Technology Services
- Location
- India, Karnataka, Bangalore India
- Posted
- 1 month ago
Job description
LTTS is looking for DV engineers with 7+ years of experience for lead role...detailed JD is below mentioned.
8/10+ of hands-on experience in SystemVerilog/UVM methodology and/or C/C++ based verification
8/ 10+ experience in IP/sub-system and/or SoC level verification based on SystemVerilog UVM/OVM based methodologies
Experience in development of UVM based verification environments from scratch
Experience in architecting and implementing Design Verification infrastructure and executing the full verification cycle
Experience with verification of ARM/RISC-V based CPU sub-systems or SoCs
Experience with IP or integration verification along with expertise of protocols like AMBA, PCIe, DDR, USB, Ethernet
Experience in EDA tools and scripting (Python, TCL, Perl, Shell) used to build tools and flows for verification environments
Experience with revision control systems like Mercurial(Hg), Git or SVN
Required skills
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