Principal Engineer, ASIC Development Engineering (RTL Design)

About the Role:

We are seeking a highly experienced and motivated Principal Engineer specialising in SoC RTL Design for System-on-Chip (SoC) solutions. As a key technical skill, you will drive the SoC Architecture, Design, and integration of complex digital systems, collaborating with cross-functional teams to deliver next-generation semiconductor products.

Key Responsibilities:

• Define and review SoC architecture and design specifications.
• Develop high-quality RTL which is synthesizable using Verilog/SystemVerilog.
• Ensure robust design methodologies, including lint, CDC, RDC and FC-Elab.
• Drive Cross-Functional Collaboration: Partner with SoC Design, Verification, Validation, DFT, Physical Design, Mixed-Signal IP, Foundry, Hardware, Firmware, and Test Engineering
• Mentor and Inspire: Provide technical leadership and mentorship to engineering teams, fostering a culture of innovation, accountability, and continuous improvement.
• Technical Excellence: Drive integration and debug efforts for subsystem and full-chip level. Analyse design trade-offs and guide design optimisations for area, performance, and power.
• Contribute to IP selection, evaluation, and integration in SoC designs.
• Communicate with Impact: Deliver clear, concise, and transparent project updates to stakeholders, ensuring alignment across all levels.