ACL Digital
1 year ago
IP Verification Engineer
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Company information
- Company
- ACL Digital
- Location
- India, Karnataka, Bangalore India
- Posted
- 1 year ago
Job description
Job Title: IP Verification Engineer – UVM verification
Exp Level: 4+ yrs
Location: Bangalore/Hyderabad
Job Description: System Verilog based UVM Functional verification, Behavioral modelling of functional blocks. System level performance verification, traffic patterns, bandwidth & latency analysis. Expertise in AXI4 bus protocol. Experience in Network On Chip (NOC) protocol. Experience in multi-master, multi-slave AXI4 use-case configurations. Knowledge of DRAM memory controllers.
Develop and execute testbenches to validate the functionality and correctness of models, as well as participate in system-level testing and debugging.
Basic Job Deliverable: Setup verification environment and bring up simulations with various simulations such as VCS / Questa / Xcellium / Riviera
SV/UVM Functional verification
Expertise in Vivado for simulation debugs
Qualification: B.E/M.E/M.Tech
Interested can Share CV to [email protected]
Required skills
- b.e
- simulations
- uvm
- vivado
- m.tech
- m.e
- vcs
- questa
- axi4
- functional verification
- system verilog
- riviera
- testbenches
- traffic patterns
- ip verification engineer
- uvm verification
- behavioral modelling
- system level performance verification
- bandwidth analysis
- latency analysis
- axi4 bus protocol
- network on chip
- noc protocol
- multi-master
- multi-slave
- dram memory controllers
- xcellium
- sv/uvm
- simulation debugs
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