Design Verification Engineer- UCIE

Position Overview We are seeking a highly skilled and experienced Design Verification Engineer with over 6 years of experience, specifically in UCIe IP and Subsystem verification, to join our innovative team. The ideal candidate will have a strong background in verification methodologies, System Verilog programming skills, excellent problem-solving skills, and the ability to work collaboratively in a fast-paced environment. Key Responsibilities: Develop and execute verification plans for UCIe IP and subsystems. Create testbenches and verification environments using System Verilog and UVM. Develop and maintain test suites to ensure comprehensive coverage. Perform simulations and debug failures. Analyze simulation results and identify root causes. Collaborate with design and architecture teams to understand specifications and provide feedback. Participate in code and test plan reviews. Contribute to the improvement of verification methodologies and tools. Stay up-to-date with the latest UCIe specifications and industry trends. Qualifications: Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field. 6+ years of experience in design verification. Strong understanding of verification methodologies, including UVM. Proficiency in System Verilog programming. Experience with UCIe protocol and its verification. Experience with PCIe protocol is a plus. Experience with scripting languages (e.g., Python, Perl). Excellent problem-solving and debugging skills. Ability to work independently and as part of a team. Excellent communication and interpersonal skills. Experience with simulation tools (e.g., VCS, QuestaSim). Benefits: Competitive salary and benefits package. Opportunity to work on cutting-edge technology. Collaborative and innovative work environment. Professional development opportunities.