Design Verification Engineer

Job description

Job Title: Design Verification Engineer Exp Level:2yrs Location: Bangalore/Hyderabad Job Description: Responsible for ensuring functional correctness of ASIC/SoC designs. Key Task: Develop and execute verification plans for complex digital designs. Methodology: Use UVM/SystemVerilog to create testbenches, write test cases, and debug failures. Coverage: Achieve functional and code coverage targets through constrained random and directed testing. Collaboration: Work with RTL designers to identify and resolve design issues. Requirements: Strong understanding of digital design principles, experience in verification methodologies, and proficiency in UVM/SystemVerilog. Benefits: Opportunity to work on cutting-edge technologies, collaboration with experienced engineers, and professional growth.

Required skills

code coverage asic test cases soc systemverilog uvm rtl testbenches verification plans digital designs constrained random testing directed testing

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