SOC DFT Engineer
SoC DFT Engineer Job Description: Scan insertion. SCAN DRC/Coverage debug. ATPG Pattern generation. Gate level simulations ( Zero delay/Timing Delay simulations). Worked on JTAG/P1500 protocols. Perl/...
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SoC DFT Engineer Job Description: Scan insertion. SCAN DRC/Coverage debug. ATPG Pattern generation. Gate level simulations ( Zero delay/Timing Delay simulations). Worked on JTAG/P1500 protocols. Perl/...
Design Verification: Experience : 4 years Location : Hyderabad and Bagalore. Must have good knowledge on the verification flows Excellent hands-on debug skills and problem solving attitude. Experience...
Experience: 4 to 12 Years.Location: Bangalore.Must have hands-on experience coding in System Verilog/UVM.Experience developing testbenches for block level or IP level verification.Experience working o...
Experience: 4 to 12 Years.Location: Bangalore.Must have hands-on experience coding in System Verilog/UVM.Experience developing testbenches for block level or IP level verification.Experience working o...
Role Overview: Job Title : PNR Lead Experience : 8 Years Work location : Bangalore Job Description: Technical Skills: Should be able to handle Full chip PnR (timing/congestion/CTS issues), understandi...
GFx IP Verification Engineer Job Description: Develop and maintain UVM-based verification environments for Graphics (GFx) IP blocks. Create comprehensive test plans based on design specifications and...
Job Discription: Strong on CXL verification, better to have CXL hands on project. 8 years of experience Interested please share your updated resume to [email protected]
Experience: 3 - 6 Years Notice period: Immediate Location: Bangalore & Hyderabad Responsibilities Mandatory Experience in Full Chip Timing . Strong background in digital IC design , including floorpla...
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