Senior Design Verification Engineer

Job description

Design Verification: Experience : 4 years Location : Hyderabad and Bagalore. Must have good knowledge on the verification flows Excellent hands-on debug skills and problem solving attitude. Experience of working in complex test-bench/model in Verilog, System Verilog or SystemC Experience of working on Functional Verification, SoC Verification, Emulation Good in programming : System Verilog, PLI/DPI interface, C/C++, PERL/Shell script, assembly language OVM/UVM Methodology knowledge and experien...

Required skills

c c++ shell script perl dpi uvm verilog Övm pli emulation functional verification system verilog systemc soc verification assembly language

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