Static Timing Analysis (STA) Engineer

Static Timing Analysis (STA) Engineer Job Summary The Static Timing Analysis (STA) Engineer will own the timing sign-off and closure for complex integrated circuits (ICs) and/or System-on-Chips (SoCs). This role involves defining and validating timing constraints, performing multi-mode multi-corner (MMMC) timing analysis, and collaborating with design and physical design teams to achieve the target operating frequency and performance metrics. Key Responsibilities Timing Sign-off and Analysis Timing sign-off and closure for complex ICs/SoCs. Develop and validate timing constraints for synthesis and STA. Perform static timing analysis using industry-standard tools. Debug timing violations and identify root causes. Implement timing closure techniques to meet performance targets. Collaborate with design and physical design teams to optimize designs for timing. Timing Constraints and Methodology Development Define and implement timing constraints for various design blocks. Develop and maintain timing analysis methodologies. Automate timing analysis flows and reporting. Ensure compliance with timing specifications and design rules. Tool and Flow Development Evaluate and select STA tools and methodologies. Develop and maintain scripts for timing analysis automation. Optimize timing analysis flows for performance and accuracy. Stay current with the latest STA tools and techniques. Team Collaboration and Communication Work closely with design, physical design, and verification teams. Communicate timing analysis results and recommendations effectively. Participate in design reviews and provide timing feedback. Train and mentor junior engineers. Qualifications Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or related field. 5+ years of experience in static timing analysis. Strong understanding of digital circuit design and timing concepts. Experience with industry-standard STA tools (e.g., PrimeTime, Tempus). Proficiency in scripting languages (e.g., TCL, Python). Experience with timing constraint development and validation. Knowledge of semiconductor manufacturing processes and design rules. Excellent problem-solving and communication skills. Experience with low-power design techniques is a plus. Experience with advanced node technologies (7nm, 5nm, etc.) is a plus. Experience with formal verification is a plus. Benefits Competitive salary and benefits package. Opportunity to work on cutting-edge technology. Collaborative and innovative work environment. Professional development and growth opportunities.