STA

Responsibilities:* Responsible for leading a team of STA engineers and closing high-frequency, lower-tech node complex designs.* Conduct full-chip timing analysis from early investigation to final implementation and tape-out.* Propose or develop timing methodologies to support the timing flow from RTL synthesis to implementation and timing closure.* Work with architects and logic designers to generate block- and full-chip timing constraints.* Analyze scenarios and margin strategies with the Synthesis & Design team.* Partner with physical design teams to close and sign off the designs through PnR (Place and Route) and ECO (Engineering Change Order) cycles.* Work with the physical design team to improve interface and clock latency.* Develop SDC constraints for blocks, partitions, and full-chip, including define constraints, IO budgeting, and merging constraints.* Collaborate with third-party IP providers to derive timing signoff requirements.
Requirements:* Bachelor's or Master's degree in Electrical Engineering or Electronics & Communications.* 3+ years of experience in STA (Static Timing Analysis).* Hands-on experience in ASIC timing constraints generation and timing closure.* Expertise and advanced knowledge of industry-standard timing EDA tools (Prime Time, StarRC, Tempus, Tweaker, etc.).* Deep understanding and experience in timing closure of various functional and test modes.* Expertise in deep-submicron processes, including Crosstalk delay, noise glitch, AOCV/SOCV/POCV, and STA.* Proficiency in industry-standard EDA tools from Cadence, Synopsys, and Mentor Graphics for Synthesis, PnR, and Signoff Closure.* Strong scripting skills using TCL, Python, or Perl for design automation and tool customization.* Excellent problem-solving and analytical skills, with a track record of delivering high-quality designs on schedule.* Outstanding communication and interpersonal skills, with the ability to collaborate effectively in a team environment.* Efficient written and verbal communication, excellent organization skills, and mentorship qualities.* Ability to work cross-functionally with various teams and be productive under aggressive schedules.* Proven ability to lead and mentor junior engineers, fostering their professional growth and development.