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(Sr./Staff) Design Verification Engineer
Job description
Description: As design verification engineer, you would be part of a passionate verification team that is constantly pushing the limits – developing and deploying state-of-the-art verification methodologies in ever-increasing design complexities, from UVM, C/C++ co-simulation, system emulation to mixed-mode simulation & formal verification. The goal is simple – to achieve zero-defect with the best and smartest approach to the large verification space. Requirements Experience in UVM verification…
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Company information
- Company
- OMNIVISION
- Location
-
Singapore
Singapore - Posted
- 6 months ago
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