NextiCron Technologies
1 month ago
SRAM Senior / Staff / Principal – Design & Layout Engineers
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Company information
- Company
- NextiCron Technologies
- Location
- India, Karnataka, Bangalore India
- Posted
- 1 month ago
Job description
#Hiring: Senior SRAM / Memory Compiler Design & Layout Engineers NextiCron Technologies is expanding its SRAM and memory compiler development team. We are looking for experienced semiconductor professionals with strong expertise in memory circuit design, compiler development, and a good understanding of custom memory layout. Locations: Bangalore, Noida, Hyderabad Employment Type: Full-time Work Mode: Flexible, based on project requirements Responsibilities
- Design and develop SRAM, ROM, and register file memory compilers.
- Work on memory architecture, read and write paths, sensing circuits, assist techniques, control logic, and design margins.
- Perform functional, timing, power, yield, and PVT analysis.
- Support memory characterization and the generation of Liberty and Verilog models.
- Contribute to memory compiler architecture, validation, and automation flows.
- Collaborate with custom layout engineers on bitcells, peripheral circuits, array integration, parasitic effects, and physical implementation.
- Review layout-dependent effects and support DRC, LVS, EM/IR, LEF, and GDS deliverables.
- Provide technical guidance and support the execution of memory compiler development projects.
- 3–15 years of hands-on experience in SRAM, embedded memory, register file, ROM, or memory compiler development.
- The position may be offered at the Senior, Staff, Principal, or Lead level, depending on the candidate’s experience and technical expertise.
- Strong understanding of memory architecture, transistor-level circuit operation, design margins, and PVT variation.
- Experience with memory characterization and deliverables such as Liberty and Verilog models.
- Good understanding of SRAM bitcell and peripheral layout, array integration, parasitic effects, DRC, and LVS.
- Hands-on experience with Cadence, Synopsys, Siemens EDA/Calibre, or equivalent semiconductor design tools.
- Experience with advanced-node or foundry-based memory development is preferred.
- Direct experience in custom memory layout would be an advantage.
Required skills
- lvs
- principal engineer
- senior engineer
- vlsi
- foundry
- gds
- design engineer
- staff engineer
- functional analysis
- control logic
- power analysis
- calibre
- cadence
- synopsys
- sram
- memory architecture
- layout engineer
- automation flows
- drc
- rom
- memory circuit design
- memory compiler
- compiler development
- custom memory layout
- register file
- sensing circuits
- design margins
- timing analysis
- yield analysis
- pvt analysis
- memory characterization
- liberty models
- verilog models
- bitcells
- peripheral circuits
- array integration
- parasitic effects
- physical implementation
- layout-dependent effects
- em/ir
- lef
- semiconductor memory design
- custom ic layout
- siemens eda
- advanced node
- embedded memory
- transistor-level circuit operation
- pvt variation
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