Sr. ASIC Design Verification Engineer – TB Architecture

Hi - We are looking for a senior ASIC Design Verification engineer who owns testbench architecture, not just tests. This role is about building scalable UVM environments and driving SoC verification from spec to silicon. Experience: 8 years (ASIC only) Location Bangalore What you will do Architect and build scalable UVM testbenches from scratch at subsystem and SoC level Own testbench architecture: structure, reuse, scalability, maintainability Define verification strategy and test plans from specification to silicon Develop and execute test cases for functional and performance verification of ASICs Collaborate with architects and engineers to ensure testbench meets requirements Provide guidance on best practices for UVM and SystemVerilog Utilize industry-standard tools such as VCS, QuestaSim, or NCVerilog