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Fidus Systems

11 months ago

Senior ASIC Verification Designer

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Company information

Company
Fidus Systems
Location
Canada, Ontario, Ottawa region, Ottawa Canada
Posted
11 months ago
View all jobs at Fidus Systems

Job description

Headquartered in Ottawa, with additional design center locations in Waterloo and San Jose, Fidus is a global leader and dynamic high-tech design firm. Fidus specializes in leading-edge electronic product development. Our hardware, software, FPGA, and signal integrity teams innovate, design, and deliver next-generation products for clients in emerging technology markets. Fidus leads in system, hardware, and embedded software design, providing a technical advantage to our global clients, from technology start-ups to established industry leaders. Our team is rapidly expanding and we are looking for a Senior ASIC Verification Designer to join our team! In this role, you will be responsible for the verification of complex ASICs, collaborating closely with design and architecture teams. You will develop and execute comprehensive verification plans, ensuring the quality and functionality of our designs. Key Responsibilities: * Develop and implement verification strategies and test plans for complex ASIC designs. * Create and maintain verification environments using industry-standard methodologies (e.g., UVM). * Write test benches and tests to verify the functionality and performance of ASICs. * Debug simulation failures and identify root causes. * Collaborate with design and architecture teams to understand design specifications and requirements. * Participate in design reviews and provide feedback on verification aspects. * Stay up-to-date with the latest verification techniques and tools. * Automate verification processes and improve efficiency. Qualifications: * Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field. * 8+ years of experience in ASIC verification. * Strong understanding of digital design and verification principles. * Proficiency in Verilog or SystemVerilog. * Experience with UVM (Universal Verification Methodology). * Experience with simulation tools (e.g., Cadence Xcelium, Synopsys VCS). * Experience with scripting languages (e.g., Python, Perl). * Excellent problem-solving and debugging skills. * Strong communication and teamwork skills. Bonus Points: * Experience with formal verification. * Experience with low-power design verification. * Experience with emulation platforms. * Familiarity with industry-standard protocols (e.g., PCIe, Ethernet). Benefits: * Competitive salary. * Comprehensive health benefits. * Paid time off. * Professional development opportunities. * Collaborative and innovative work environment.

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