Senior ASIC / RTL / Logic Design Engineer – Memory Controller Design

TITLE: Senior ASIC / RTL / Logic Design Engineer – Memory Controller Design LOCATION: GREATER HYDERABAD AREA ABOUT COMPANY: Founded by highly respected Silicon Valley veterans, we are a startup headquartered in US with its design centre established in Santa Clara, California. / Hyderabad/ Bangalore JOB DESCRIPTION: We are seeking a highly experienced, innovative, and technically strong ASIC / RTL / Logic Design Engineer to join our Memory Controller Design Centre of Excellence (CoE). This role is responsible for designing and developing high-performance memory controllers using advanced digital logic techniques. The ideal candidate will have expertise in Verilog or VHDL, with experience in designing and verifying complex digital circuits. Strong understanding of memory controller architecture, including DDR4/5, LPDDR4/5, and GDDR6. Experience with Synopsys VCS, Cadence Genus, or Mentor Graphics QuestaSim is a plus. Familiarity with scripting languages such as Python or Tcl is also desirable. The successful candidate will be expected to work closely with cross-functional teams, including hardware engineers, software developers, and test engineers to deliver high-quality memory controllers that meet customer requirements. This role offers the opportunity to work on cutting-edge technology, collaborate with a talented team of engineers, and contribute to the development of innovative memory controller designs.