RISC-V Manager / HW Engineering Manager

Working for a cutting edge semiconductor company, based in Barcelona I have an exciting opportunity as HW Engineering Manager. You will be tasked with managing a team who are developing a RISC-V SOC. Applicants can come from an architecture, digital design or verification background. MUST HAVE - Deep understanding of ASIC, FPGA and SOC development processes. Must have experience: Degree / Masters / PhD in electronics / micro-electronics, physics or similar field 10 years' experience of full chip development, including RTL design, synthesis, place and route, timing closure and power management. Experience with RISC-V architecture is a must. Familiarity with Linux and/or other operating systems is an advantage. MUST HAVE - Strong leadership skills to manage a team of engineers. Ability to work in a fast-paced environment and prioritize tasks effectively. Excellent communication and interpersonal skills. Ability to travel occasionally for business purposes.