Memory Layout Engineer

Memory Layout Engineer Location: Bengaluru Experience Required: 3 Years Employment Type: Full-Time Job Summary: We are seeking an experienced and detail-oriented Memory Layout Engineer with 3 years of hands-on experience in custom layout design and verification of memory IPs (SRAM, ROM, CAM, etc.). The ideal candidate will have a strong background in advanced technology nodes and be well-versed in layout tools and methodologies. Key Responsibilities: Create and optimize transistor-level custom layouts for memory IPs (SRAM, ROM, CAM, etc.). Perform layout verification (LVS, DRC, ERC) to ensure design correctness and manufacturability. Conduct post-layout simulations and analysis (extraction, parasitic RC) to optimize performance. Collaborate with circuit designers and other engineers to meet design specifications and performance goals. Develop and maintain layout design methodologies and guidelines. Participate in design reviews and provide feedback on layout related issues. Stay up-to-date with the latest advancements in memory design and layout techniques. Required Skills and Qualifications: Bachelor's or Master's degree in Electrical Engineering or a related field. 3+ years of experience in custom layout design and verification of memory IPs. Strong understanding of CMOS transistor-level design and layout principles. Proficiency in layout tools such as Cadence Virtuoso, Mentor Graphics Calibre, or similar. Experience with layout verification tools (LVS, DRC, ERC). Knowledge of post-layout simulation and analysis tools. Familiarity with advanced technology nodes (e.g., 28nm, 14nm, 7nm, and below). Excellent problem-solving and communication skills. Ability to work independently and as part of a team. Preferred Skills: Experience with scripting languages such as Python or Perl. Knowledge of memory design architectures. Familiarity with reliability and variability analysis. Benefits: Competitive salary Health insurance Paid time off Professional development opportunities