Lead ASICVerification Engineer (SoC & Large Subsystems, UVM & TB Architecture)

We are looking for a Senior / Principal ASIC Design Verification Engineer to lead hands-on verification of complex SoCs or large subsystems, owning execution from verification planning through tapeout and silicon correlation. This role requires deep UVM expertise and strong closure discipline. Job Description: Own end-to-end verification at subsystem or SoC level, including authoring verification plans from specs and micro-architecture and building reusable UVM/SystemVerilog environments from scratch. Develop and maintain comprehensive testbenches for complex systems using UVM and SystemVerilog. Collaborate with cross-functional teams to identify and prioritize verification requirements. Utilize TB architecture to drive verification planning and execution. Ensure high-quality, efficient, and scalable verification flows that meet project timelines and budgets. Provide technical guidance and mentorship to junior engineers. Stay up-to-date with industry trends and advancements in UVM and SystemVerilog.