SmartSoC Solutions Pvt Ltd
3 weeks ago
Layout Design Engineer
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Company information
- Company
- SmartSoC Solutions Pvt Ltd
- Location
- India India
- Posted
- 3 weeks ago
Job description
About the Company
SmartSOC Solutions is dedicated to delivering cutting-edge semiconductor solutions. Our mission is to innovate and excel in the field of advanced technology, fostering a culture of collaboration and excellence.
Qualifications
- 4 to 8 years of relevant experience in Analog/ Memory Layout Design.
- Mandatory: Hands-on experience with FinFET technology or Samsung/ TI/ TSMC Foundry process technologies.
- Strong experience in advanced technology nodes such as 2nm, 3nm, 5nm, or 7nm.
- Experience in custom analog layout, DRC/LVS/ERC/PEX closure, and layout optimization.
- Immediate joiners or candidates who can join within a short notice period are preferred.
Responsibilities:
- Develop high-quality full-custom analog and mixed-signal layouts.
- Perform floorplanning, device matching, routing, shielding, and optimization for analog circuits.
- Execute layout verification including DRC, LVS, ERC, and PEX closure.
- Ensure layout quality while meeting performance, power, area, and reliability requirements.
- Collaborate with circuit designers to resolve layout-related issues and optimize design performance.
- Work with advanced process technologies including FinFET nodes (2nm, 3nm, 5nm, and 7nm).
- Perform parasitic-aware layout optimization and support post-layout verification.
- Ensure compliance with foundry design rules and best layout practices.
- Participate in design reviews and contribute to silicon bring-up support when required.
Required skills
- routing
- design reviews
- performance optimization
- shielding
- power optimization
- layout optimization
- floorplanning
- analog layout design
- reliability requirements
- area optimization
- post-layout verification
- memory layout design
- finfet technology
- samsung foundry process technologies
- ti foundry process technologies
- tsmc foundry process technologies
- 2nm technology nodes
- 3nm technology nodes
- 5nm technology nodes
- 7nm technology nodes
- custom analog layout
- drc closure
- lvs closure
- erc closure
- pex closure
- mixed-signal layouts
- device matching
- circuit designers
- parasitic-aware layout optimization
- foundry design rules
- best layout practices
- silicon bring-up support
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