FPGA Engineer

RTL FPGA Design Engineer Experience: 2 to 4 Years Location: Hyderabad, India. Job Description: Minimum of 2 years of RTL design and development experience, preferably in a customer facing role Minimum of 2 years of experience in FPGA Verilog design, technology, and tools Experience in developing RTL designs in one or more of the following technologies: PCIe, Ethernet, TCP/IP, Packet processing, USB, etc. Proficient in debugging RTL code using simulation tools Excellent ability to analyze and isolate issues in complex digital circuits Strong understanding of digital logic principles and their application in FPGA design Familiarity with VHDL language is a plus Experience working with FPGA development boards such as Xilinx or Intel is an asset Ability to work effectively in a team environment and collaborate with cross-functional teams Strong communication skills, both written and verbal.