Digital Verification UWB Expert (m/f/d)

Develop verification specifications and plans for complex SoCs and IP blocksLead and execute verification at module, cluster, and top-levelDesign and implement UVM-based test environments for functional, gate-level, and low-power simulationsDevelop reusable Verification IP (VIP) using the UVM frameworkIntegrate reference models and VIP components into SystemVerilog and SystemC testbenchesDevelop reference models in SystemVerilog, Matlab, or PythonExecute and analyze regression simulations and monitor coverage progressDebug digital modules using advanced simulation and formal verification toolsContribute to system-level simulations and virtual prototyping using SystemVerilog UVM and SystemCUnderstand system and IP requirements and specifications and derive corresponding test strategiesVerify UWB-related digital designs, including protocol logic, timing behavior, and RF-related digital signal processing paths Degree in Electrical Engineering, Computer Engineering, Computer Science, Physics or a related fieldStrong experience with SystemVerilog and UVM, ideally including SystemCProven background in digital verification, including simulation and formal methodsPractical experience in UWB (Ultra-Wideband) verification is mandatoryFamiliarity with SoC verification environments and EDA toolsKnowledge of Matlab and/or Python is beneficialStrong analytical thinking, problem-solving skills and attention to detailEnjoys collaborative work with design, system and lab teams A very renowned companyRemote Work possible Our many years of recruitment experience and our expert knowledge of the engineering job market make us a strong partner for engineers and technicians. We maintain close relationships with customers across all industries and therefore can provide engineering specialists with exciting projects and attractive job opportunities, drawing on your personal interests and experience. As your professional companion, we support you throughout the entire process, from the first contact to the first day on your new job – all this completely free of charge. Register now and look forward to many interesting and suitable positions and projects.

Responsibilities

Develop verification specifications and plans for complex SoCs and IP blocksLead and execute verification at module, cluster, and top-levelDesign and implement UVM-based test environments for functional, gate-level, and low-power simulationsDevelop reusable Verification IP (VIP) using the UVM frameworkIntegrate reference models and VIP components into SystemVerilog and SystemC testbenchesDevelop reference models in SystemVerilog, Matlab, or PythonExecute and analyze regression simulations and monitor coverage progressDebug digital modules using advanced simulation and formal verification toolsContribute to system-level simulations and virtual prototyping using SystemVerilog UVM and SystemCUnderstand system and IP requirements and specifications and derive corresponding test strategiesVerify UWB-related digital designs, including protocol logic, timing behavior, and RF-related digital signal processing paths

Benefits

A very renowned companyRemote Work possible