Digital - IC Design Engineer - Digital Physical - III (m/f/d)

Implementing Cadence AI functions in the design flowDevelop and refine timing constraints and collaborate with front-end teams to address critical timing paths.Run Static Timing Analysis (STA), resolve timing violations, and ensure sign-off readiness.Implement and optimize clock-tree structures for robust performance.Perform RTL-to-gate synthesis aligned with MCU architecture requirements.Optimize designs to meet stringent low-power goals.Support SoC floorplanning and contribute to physical distribution strategies.Conduct routing, signal-integrity analysis, IR-drop evaluation, and implement corrective measures.Select and apply technology libraries, transforming RTL functionality into efficient structural implementations.Participate in the physical verification of timing, power, and overall design integrity.Develop automation scripts (TCL/Perl/Python) to enhance and streamline the physical design Proficiency with the Cadence Physical Design flowStatic Timing Analysis and timing closureClock-tree implementationTiming-constraint developmentLow-power optimization techniquesRTL-to-gate synthesisSignal-integrity and IR-drop analysisFloorplanning and manual physical layoutSolid scripting abilities (TCL, Perl, or Python).Comfortable working in UNIX/Linux environments. Remote possibility Our many years of recruitment experience and our expert knowledge of the engineering job market make us a strong partner for engineers and technicians. We maintain close relationships with customers across all industries and therefore can provide engineering specialists with exciting projects and attractive job opportunities, drawing on your personal interests and experience. As your professional companion, we support you throughout the entire process, from the first contact to the first day on your new job – all this completely free of charge. Register now and look forward to many interesting and suitable positions and projects.

Responsibilities

Implementing Cadence AI functions in the design flowDevelop and refine timing constraints and collaborate with front-end teams to address critical timing paths.Run Static Timing Analysis (STA), resolve timing violations, and ensure sign-off readiness.Implement and optimize clock-tree structures for robust performance.Perform RTL-to-gate synthesis aligned with MCU architecture requirements.Optimize designs to meet stringent low-power goals.Support SoC floorplanning and contribute to physical distribution strategies.Conduct routing, signal-integrity analysis, IR-drop evaluation, and implement corrective measures.Select and apply technology libraries, transforming RTL functionality into efficient structural implementations.Participate in the physical verification of timing, power, and overall design integrity.Develop automation scripts (TCL/Perl/Python) to enhance and streamline the physical design

Benefits

Remote possibility