Design for Test Engineer (DFT)

Hiring for: A leading global IT Services & Consulting firm (Top 5 in India)

Experience: 7 years to 14 years

Location: Bangalore

Work Mode: Hybrid

Notice Period: Immediate to 60Days

Mandatory Skills

• Design for Test
• (DFT)Scan Compression
• Automatic Test Pattern Generation
• (ATPG)Silicon Validation

Roles & Responsibilities

• Develop and implement DFT architecture for complex SoC/ASIC designs.
• Design and integrate scan chains, scan compression, and boundary scan (JTAG) features.
• Generate and validate ATPG patterns for stuck-at, transition, and other fault models.
• Perform DFT verification, coverage analysis, and debug to achieve high manufacturing test coverage.
• Collaborate with RTL, Design, Physical Design, and Verification teams to ensure seamless DFT implementation.
• Support silicon bring-up, silicon validation, and production test activities issues.
• Analyze silicon test failures and work with cross-functional teams to identify and resolve
• Optimize DFT methodologies to improve test quality, reduce test time, and minimize test costs.
• Ensure compliance with industry-standard DFT methodologies and best practices.
• Prepare and maintain DFT documentation, test plans, and implementation reports.

Preferred Qualifications

• Strong understanding of SoC/ASIC design flow.
• Experience with scan insertion, scan compression, ATPG, and fault coverage analysis.
• Hands-on experience in silicon validation and post-silicon debug
• Excellent debugging, analytical, and problem-solving skills.
• Strong communication and collaboration abilities.

Interested candidates, please share your updated resume to [email protected]