ASIC RTL Design Engineer (SoC/Subsystem)

We are hiring a Senior / Principal ASIC RTL Design Engineer to take full ownership of complex SoC or large subsystem RTL, driving designs from micro-architecture through tapeout and silicon bring-up. This role demands strong hands-on RTL expertise and deep collaboration across design, PD, and validation teams. Job Description: Own end-to-end RTL development for SoC-level or large subsystem blocks, from micro-architecture definition to tapeout and bring-up Develop high-quality synthesizable SystemVerilog/Verilog code with a focus on power efficiency, area optimization, and performance. Collaborate closely with cross-functional teams including design, PD, and validation engineers to ensure successful project execution. Drive the RTL development process from concept to silicon, ensuring timely delivery of high-quality designs. Provide technical guidance and mentorship to junior engineers, promoting knowledge sharing and best practices within the team. Stay up-to-date with industry trends and advancements in ASIC design, and apply this knowledge to continuously improve design quality and efficiency. Requirements: Bachelor's or Master's degree in Electrical Engineering, Computer Science, or related field 8+ years of experience in RTL design for SoC-level or large subsystem blocks Strong hands-on expertise in SystemVerilog/Verilog, with a focus on power efficiency, area optimization, and performance Experience with ASIC design tools such as Synopsys VCS, Cadence Genus, or Mentor Graphics QuestaSim Familiarity with scripting languages like Python or Tcl Knowledge of digital design principles, including clock domain crossing, reset handling, and synchronization techniques Strong problem-solving skills, with the ability to debug complex RTL issues Excellent communication and collaboration skills, with the ability to work effectively in a team environment Benefits: Competitive salary and benefits package Opportunities for professional growth and development within a dynamic company culture Collaborative and inclusive work environment with a diverse group of talented engineers