Analog Layout Engineer

Analog Layout Engineer Required Qualifications: Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field. 4 years of experience in analog layout design with a focus on TSMC 7nm, 5nm, and 3nm process technologies. Proficiency with Cadence Virtuoso, Mentor Graphics, Synopsys IC Compiler, or equivalent analog layout tools. Hands-on experience with TSMC PDKs and process technologies for 7nm, 5nm, and 3nm nodes. Strong knowledge of analog circuit design principles, including noise analysis, signal integrity, and power integrity. Experience with layout optimization techniques, such as DRC, LVS, and ERC. Familiarity with IC design flows, including design entry, simulation, and verification. Strong understanding of semiconductor manufacturing processes and their impact on IC design. Ability to work effectively in a team environment and communicate complex technical information to both technical and non-technical stakeholders. Strong analytical and problem-solving skills, with the ability to work independently and prioritize tasks effectively.