AI Chip Architecture Engineer – Hardware/Software Co-Design

Responsibilities Responsibilities · Define and evaluate architectural features for next-generation AI inference chips. · Analyze Transformer and LLM workloads to identify performance, power, area, memory, and latency bottlenecks. · Explore AI accelerator architectures and microarchitectures, including compute arrays, memory hierarchy, NoC, DMA, scheduling, and dataflow. · Work on hardware-software co-design for LLM inference, including operator mapping, tiling, memory planning, and compiler-guided optimization. · Collaborate with software engineers to develop optimized AI models for the target architecture. · Develop and maintain documentation of the chip's architecture, including block diagrams, timing diagrams, and functional descriptions. · Participate in design reviews and provide input on the overall design direction. · Work closely with cross-functional teams, including software development, verification, and manufacturing.